During semiconductor production, the electrical die sorting (EDS) process tests the electrical characteristics of chips on wafers. This stage is crucial to ensure reliable devices at high yields. However, EDS is a complex process—one that can cause significant slowdowns during manufacturing.
Rohm’s production facility in Malaysia
To address this complexity, Rohm has successfully collaborated with Quanmatic, a startup specializing in quantum technology, to optimize the EDS process in semiconductor production. The groups have recently met certain production efficiency milestones, allowing them to move their new technique into full-scale production in 2024.
Rohm and Quanmatic Team Up
Rohm and Quanmatic began collaborating in early 2023 with the aim of applying quantum technology to the EDS process.
Quantum technology, particularly quantum annealing methods, has been gaining traction in various industries for solving combinatorial optimization problems. In semiconductor manufacturing, where the number of possible process combinations increases exponentially, quantum technology can find optimal solutions that were previously unattainable with classical computing methods.
Rohm and Quanmatic’s prototype combines Quanmatic’s quantum computing technology with Rohm’s extensive knowledge and data.
The EDS process
Testing in Rohm’s factories demonstrated significant improvements in key performance indicators like utilization and delivery delay rates, along with reduced computation time.
What Is Electrical Die Sorting?
Electrical die sorting is an essential process in semiconductor manufacturing, strategically positioned between the fabrication step and the packaging phase. It primarily aims to enhance semiconductor yield rates by ensuring each chip meets quality standards before proceeding to subsequent stages. EDS involves several critical steps.
Electrical Test and Wafer Burn-In
The electrical test (ET) involves measuring integrated circuit components’ DC voltage and current characteristics to assess nominal operation. Following the ET, the wafer burn-in process heats the wafer and subjects it to AC and DC currents to identify defects, weaknesses, and potential issues, significantly improving product reliability.
Hot/Cold Test
This stage tests the chips at temperatures varying from the norm to identify defective ones. Repairable chips are marked for later correction, ensuring they function flawlessly across different temperature ranges.
Repair/Final Test
Chips deemed repairable in the hot/cold test undergo repairs. A final test confirms the effectiveness of these repairs.
Inking
This final step of the EDS process involves marking defective chips, including those failing the hot/cold test, improperly repaired, or incomplete on the wafer. Defective chips are excluded from assembly, conserving materials, equipment, time, and labor.
Full-Scale Production
EDS is vital for sorting defective semiconductor chips at the wafer level, addressing issues from fabrication or design steps, and streamlining the efficiency of packaging and testing phases. By removing defective chips early, EDS significantly contributes to semiconductor productivity, with yield being a key performance indicator.
This news marks the first instance of quantum technology being employed in a large-scale semiconductor manufacturing facility. With full-scale implementation slated for April 2024, the companies hope to enable a semiconductor supply chain that is continually optimized on a daily basis for better yields and greater throughput.
All images used courtesy of Rohm Semiconductor
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